1. Field of the Invention
The present invention relates to a system and method for managing the Compact Peripheral Component Interconnect (CPCI) buses in a multi-processing system, and more particularly to a system and method for improving performance by using multiple system slots on a CPCI bus in a multi-processing system.
2. Background of the Related Art
Generally, there are eight slots for the system clock of 33 MHz and five slots for the system clock of 66 MHz in the CPCI of the related art. Of these, the eight slots of 33 MHz will be explained in the following. As shown in FIG. 1, the related art standard CPCI buses each of which connects the eight slots by using the first pin (P1) or the second pin (P2).
Also, as shown in FIG. 1, one CPCI bus has eight slots (SLOT 0˜SLOT 7) and signals related to the CPCI buses are connected respectively to P1 and P2 throughout the relevant slots (SLOT 0˜SLOT 7). The third pin to the fifth pin (P3˜P5) provide routes for signal transmission between the front card and the rear card. Sometimes, the fourth pin (P4) accommodates H.110 bus.
Accordingly, the system slot usually is either the leftmost slot or the rightmost slot. For example, the slot located at either end of the slots (SLOT 0 or SLOT 7) may be used as the system slot. Further, the location of the respective system slot pins of CPCI bus signals is previously determined. Because such location is different from the location of other slots (SLOT 1˜SLOT 6), the system slot can not be changed once it is determined. Also, because only one slot is assigned as the system slot, there is only one system board on a CPCI bus. The other slots are peripheral slots and a variety of peripheral cards may be located at the peripheral slots according to various system structure requests.
Additionally, all bus arbitrations are conducted by the system board and all peripheral cards may transmit and receive messages only through the system board. For example, peripheral cards do not exchange messages directly among themselves. Also, bus requests from all of the slots and bus grants for all the relevant slots are concentrated on the system slot. Thus, in the related art, the system slot supplies clocks to all of the other slots and performs an interrupt process by receiving an interruption signal from the each relevant slot.
In the CPCI bus of the related art, as illustrated in FIG. 1, there is one system slot, on which all operations of the CPCI bus are concentrated. First, the system board accesses the configuration spaces of the peripheral boards of other slots and reads information regarding each peripheral board. Then, the system board activates the driver for each peripheral board based upon the information read with respect to each relevant peripheral board. All the peripheral slots are given relevant address areas on the CPCI bus according to the locations of the slots. Through this action, a peripheral board may recognize that it has been selected.
All the peripheral boards use a PCI bridge in order to map their local addresses to the address areas allotted on the Peripheral Component Interconnect (PCI) bus.
All operations on a CPCI bus are synchronized through the clock signal provided by the system board. Each of the peripheral boards may obtain the right to use the bus among all the boards on the CPCI bus through the bus request defined in accordance with the CPCI bus specification. Of all the boards on the CPCI bus, the system board takes the role of granting and arbitrating the bus occupancy, by responding to a peripheral board with bus grant signal with respect to a certain bus request. The system board grants the right to use the bus to the board of the slot requesting the bus occupancy.
Each peripheral slot has an interruption signal which has been determined by the CPCI specification. The PCI bridge is set for the assertion of interruption signals and for the system board's observation of the current interruption signal situation. Thus, upon the receipt of an interruption signal, the system board accesses the relevant address and determines the type of interruption.
Thus, in the mode of operations of the related art, because there is only one system board on one bus, it is difficult to satisfy the reliability standard required in a multi-processing system. More specifically, in the related art, the system board on a CPCI bus may not be extended because there is only one system board on one CPCI bus and because all the other slots are used for peripheral boards. Thus, if the system board is in an abnormal state, the other slave boards on the CPCI bus cannot discharge their functions accordingly.
Further, because the CPCI bus of the related art always has a certain number of slots assigned for slave boards, if there are only a few slave boards, there may be wasted space and thus the system integration may be degraded.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.